1. Field of the Invention
Example embodiments of the present invention relate to a data processing system capable of operating in a synchronous mode and an asynchronous mode by processing data and control information as a data packet and a data processing method for receiving and transferring data.
2. Description of the Related Art
Recently, there have been developments in processes and systems for providing efficient network services between digital devices such as computer terminals, peripheral devices, communication devices and mobile communication systems.
These digital devices may include a computer system for data processing. The computer system may include a central processing unit (CPU) that performs various operations and controls important system operations, and a plurality of sub-systems, e.g., a plurality of data processing systems, that may perform core functions associated with the CPU.
Each of the data processing systems may be coupled to each other with a point-to-point connection or a data bus. These data processing systems perform data packet transfers through the point to-point connection or the data bus. Further, these data processing systems may employ a first in first out (FIFO) method for data processes associated between the data processing systems at least partially because the FIFO method may be advantageous for performance evaluation, and may describe data flow between the data processing systems in view of a top layer.
FIG. 1 is a schematic diagram illustrating an example of a conventional data processing systems coupled according to a point-to-point configuration.
As shown in FIG. 1, a first data processing system 10, a second data processing system 20 and a third data processing system 30 may include a first FIFO 11, 21 and 31 for data inputs and a second FIFO for 12, 22 and 32 data outputs, respectively. The three data processing systems 10, 20 and 30 in FIG. 1 are coupled in a point-to-point configuration.
A first FIFO 11 for data inputs of a first data processing system 10 may be coupled to a second FIFO 22 for data outputs of a second data processing system 20 and may be coupled to a second FIFO 32 for data outputs of a third data processing system 30.
A first FIFO 21 for data inputs of the second data processing system 20 may be coupled to a second FIFO 12 for data outputs of the first data processing system 10, and may be coupled to the second FIFO 32 for data outputs of the third data processing system 30.
A first FIFO 31 for data inputs of the third data processing system 30 may be coupled to the second FIFO 12 for data outputs of the first data processing system 10, and may be coupled to the second FIFO 22 for data outputs of the second data processing system 20.
Each of the first FIFOs 11, 21 and 31 for data inputs may be directly coupled to each of the second FIFOs 12, 22 and 32 for data outputs. In a conventional point-to-point configuration using FIFOs, providing connection lines between the FIFOs and/or data processing systems increases in complexity as the number FIFOs and/or data processing systems increase. This is one disadvantage of the conventional point-to-point configuration as described above. Further, data processing systems coupled in a conventional point-to-point configuration require a data arbitration process to determine a source of a received and/or input data packet.
FIG. 2 is a block diagram illustrating conventional data processing systems coupled in a data bus configuration.
As shown in FIG. 2, a first data processing system 40, a second data processing system 50, and a third data processing system 60 may be coupled to one another through a data bus 70.
As compared with a conventional point-to-point configuration, the connection lines between three data processing systems shown in FIG. 2 are less complex.
Still further, a data arbitration process required for the three data processing systems 10, 20 and 30 in FIG. 1 may not required for the three data processing systems 40, 50 and 60 shown in FIG. 2 because a bus master may be equipped in one of the three data processing systems 40, 50 and 60. In light of the above, a data bus architecture as shown in FIG. 2 is implemented for most conventional computer systems.
Conventionally, data processing systems 40, 50 and 60 may include interface logic to interface with a data bus 70. However, if interface logic is mixed with data processing logic for a core function of data processing systems 40, 50 and 60, it may be difficult to perform error detection, maintenance, and/or reuse of the logic. Accordingly, an interface logic module may be configured separately from a core function of data processing systems 40, 50 and 60.
FIG. 3 is a block diagram illustrating a structure of a conventional data processing system shown in FIG. 2.
Referring to FIG. 3, a conventional data processing system may include a data processing module 42 for performing a core data processing function, and a data interface module 44 for interfacing the data processing module 42 with a data bus 70.
A data interface module 44 may include an interface control logic 45, a write FIFO 46 and a read FIFO 47. An interface control logic 45 may interface control data for data transfer between a data processing module 42 and/or a data bus 70. A write FIFO 46 may load data provided from a data processing module 42 and may output the loaded data using a FIFO method in response to a request from a data bus 70. A read FIFO 47 may load data provided from a data bus 70 and may output the loaded data using a FIFO method in response to a request from a data processing module 42.
Control data may include command data and/or state data that is associated with controls during data processing. Actual data may include target data and address data except the control data.
Conventionally, an interface between a data processing module 42 and an interface control logic 45 is not standardized at least in part because control data is not standardized in a conventional data processing system 40.
As logic compatibility is decreased, reusability is decreased and maintenance may become difficult.
Due at least in part to the above-described deficiencies in a conventional system of connecting a plurality of data processing systems as shown in FIG. 2, an operating speed of a data processing module 42 may depend on an operating speed of a data bus 70. A read FIFO 46 and/or a write FIFO 47 may perform a clock conversion, but an interface control logic 45 may not perform clock conversion due to a complex circuit structure of the interface control logic 45.
Accordingly, a data interface module 44 may use a clock CLK identical with a clock CLK of a data bus 70 due to structural features of the data interface module 44, and an operating speed of the data processing module 42 is downwardly adjusted to match the operating speed of the data interface module 44.
Accordingly, despite high performance capabilities of a data processing module 42, a data processing system 40 may not achieve full performance due at least in part to a downward adjustment of the operating speed of the data processing module 42.
A conventional data interface module 44 may be suitable for a synchronous interface, but is not suitable for an asynchronous interface.
Conventionally, when an operating speed of a data processing module 42 is different from an operating speed of a data bus 70, an extra device may be employed to support an asynchronous interface. For example, a bus wrapper may be added to a conventional data system for supporting an asynchronous interface between an output end of a data processing system 40 and a data bus 70. However, there is excessive interface overhead in a bus wrapper. In other words, because an interface protocol of a data processing system 40 is, in most cases, different from an interface protocol of a data bus 70, the bus wrapper simultaneously handles clock interfaces and protocol interfaces. Thus, a ratio of the overhead occurring in the bus wrapper may be increased.